Sony PCM-2500A/B DAT recorder

[Blue Jinn]

Wondering if anyone has one of these, knows anything about it. Looking at the schematic, it looks like the anlalog balanced ins on the B module simply attenuate and unbalance and send an unbalanced analog signal over rca (also has some emphasis circuitry too). So I should be able to just use the unbalanced ins right? (Keeping the clock signal over BCN from the B module)

Taking this one step further, and ignoring the digital i/o on the B module the only other thing is the clock. I'm assuming therefore I can use a different clock and use the A module by itself?

As for the B module's clock and digital I/O, it looks like the A/D is in the A module, so the B module would seem to be only useful by itself as an external clock (and a 2 channel +4 balanced to -10 unbalanced converter -- pin 2 hot by the way). There are no external terminators on the clock signal, so I'm also assuming I can't just use a three way adapter on the A module and send the clock somewhere else, or can I?

However, I don't see why I couldn't use the clock module with, e.g. a sound card and an external A/D/D/A that accept external clocks? (Don't know how good the clock is, or what 128FS means....)

 

[mshilarious]

You're tossing around a lot of different concepts. 128Fs means the clock needs to be 128x the desired sample rate; for example, 5.6448mHz for 44.1kHz, or 6.144mHz for 48kHz. That is not the same as a word clock, which runs at sample rate. A device designed to accept external clock will have a PLL circuit that locks onto the incoming sample rate word clock and adjusts its internal bit clock (or master clock) to match--which is running at the higher rate, 64x or 128x or 256x or whatever.

Read this:

http://en.wikipedia.org/wiki/I²S


As for termination, you may or may not see internal terminations based upon trace length. That is no indication of whether or not the clock signal is capable of driving an output. Usually that would be handled with a level converter and dedicated driver.

 

[Blue Jinn]

Thanks,

I'm reasonably certain I can bypass the balanced I/O as even in the schemo the balanced in circuitry is labeled "attenuator" but the box is bulky with the B module, so I was just wondering if I could eliminate the B box altogether and use just the rca i/o and an external clock (I have a couple of boxes that can provide a master clock.)

What I'm getting is that the sync signal is 128x the sampling freq, so it is expecting 5.6448mHz for 44.1kHz, or 6.144mHz for 48kHz as you indicated. If I'm also understanding this correctly, then a word clock out from another box, isn't going to be that, it's going to be the sampling freq, so I can't lock to that. So question is where do I find a clock that is 5.6448mHz for 44.1kHz, or 6.144mHz for 48kHz? Or is the master clock going to be a multiple of sampling freq already, with the conversion occuring at the gear?

 

[mshilarious]

What I'm getting is that the sync signal is 128x the sampling freq, so it is expecting 5.6448mHz for 44.1kHz, or 6.144mHz for 48kHz as you indicated. If I'm also understanding this correctly, then a word clock out from another box, isn't going to be that, it's going to be the sampling freq

Correct.

so I can't lock to that.

It's not a question of locking. A PLL can "lock" to it; a converter chip will simply be expecting a much faster clock, and will likely fail to work at all with a sample rate clock.

So question is where do I find a clock that is 5.6448mHz for 44.1kHz, or 6.144mHz for 48kHz?

You would have to build one. This is not a trivial task. You could start by reading this:

http://focus.ti.com.cn/cn/lit/an/scaa088/scaa088.pdf