L2 cache size on processor, does it matter for DAW?

  • Thread starter Thread starter James Argo
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James Argo

James Argo

Fancy Rock N' Roll
Most DAW users use regular P4 over Celeron, because it's L2 cache size. Does it realy matter for DAW? I'm about to build new PC, and the guy on the store effers me options P4 with 512k L2 cache, or 1MB L2 cache. I know, the bigger=the better. But why? What good does it do for DAW applications (MIDI sequencing stuff, audio recording, plugins, sampling, mixing, mastering, etc).



Thanks!
;)
Jaymz
 
Bigger not always better.
The cache is a very good thing provided it holds the right data, if not it could actually slow things down being bigger - takes longer to refill.
Processes like reverb and mp3 encoding will probably involve a fairly predictable sequence of instructions so benefit from the big cache, however there is probably still a law of diminishing returns for general processing. Many people though that clock for clock, the P4 wasn't quicker than a P3 and the blame was placed on the larger cache. Increasing clock speeds for P4 seems to have regained the advantage for it.
 
Jim Y said:
Bigger not always better.
The cache is a very good thing provided it holds the right data, if not it could actually slow things down being bigger - takes longer to refill.
I can't really think of an example where refilling cache would slow things down. It's way faster than both system memory and the bus. I'd say it's fairly safe to say that more cache is better.
Many people though that clock for clock, the P4 wasn't quicker than a P3 and the blame was placed on the larger cache.
This has more to do with the P3 and P4 being entirely different cores and has nothing to do with the P4 having more cache. Just look up some same clock P4 vs. Celeron benchmarks to see the value of cache.
 
elevate said:
I can't really think of an example where refilling cache would slow things down. It's way faster than both system memory and the bus. I'd say it's fairly safe to say that more cache is better.

I could see that argument being made for... say a software-based disk cache, but you're right that it doesn't apply for hardware caches. It generally takes roughly the same amount of round-trip time to fetch a byte as it does an entire cache line....

elevate said:
This has more to do with the P3 and P4 being entirely different cores and has nothing to do with the P4 having more cache. Just look up some same clock P4 vs. Celeron benchmarks to see the value of cache.

IIRC, it has a lot to do with more performance loss due to pipeline flushes as a result of having a much longer pipeline on the P4 (which was necessary in order to be able to clock it up to the current speeds). Were it not for the larger cache, the P4 would almost certainly have gotten its @$$ handed to it by the P3 initially.
 
elevate said:
I can't really think of an example where refilling cache would slow things down. It's way faster than both system memory and the bus. I'd say it's fairly safe to say that more cache is better.

This has more to do with the P3 and P4 being entirely different cores and has nothing to do with the P4 having more cache. Just look up some same clock P4 vs. Celeron benchmarks to see the value of cache.

An interesting example is that my Gateway 1.33Ghz Celeron laptop, with 256KB L2, kicks the crap out of my dad's 1.8Ghz 256KB L2 Pentium 4.

It's just because the P4 has a longer pipeline, and even though the clock on the Celeron is lower, it's more efficient since it's based on a PIII.

It's a great chip, for its time.
 
Generally more cache is better but if you're looking at the P4 Prescott for the extra cache, you'll pay a noise penalty as they run a lot hotter than the ordinary P4s.
Unless go you liquid cooling
 
I thought L2 WAS the "Pipeline Cache". So what's with the "it's not the cache it's the pipeline" answers?
 
L2 cache is just like L1 cache. What the computer does is when it needs to access memory it first looks in L1 cache. If the data needed is there the cpu continues on. If not it looks in L2 cache for the data. Accessing data in cache is much quicker that going out to the RAM.

look here: http://en.wikipedia.org/wiki/CPU_cache
under Multi Level caches

The pipeline refers to how the cpu actually works. Basically you have a number of instructions at different stages on the cpu. By doing this you increase the throughput of the cpu. The problem with this is when the cpu gets an interrupt it has to push everything out of the pipeline, deal with the interrupt, then push everything back through again. This is why the P3 performs better against an older P4, because the pipeline is shorter so not as much time is wasted when the pipeline is flushed...

Umm, if I'm wrong someone correct me. This stuff is kinda new to me so yeah.
 
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