Honestly....
Word Clock and SPIDF are not the same thing the way I understand it. Spidf does indeed have clocking info embedded in the digital stream which will in fact allow the the interface and the the pre to synchronize.
I wouldn't go so far as to use the word "info" to describe the clock, but yes. Word clock is a series of pulses, one per sample (IIRC), that keep two units sample-accurate with respect to one another.
By contrast, the very act of sending digital data in a serial format (one bit followed by the next) necessitates some sort of bit clock in order for the receiver to figure out where one bit ends and one bit ends. There are various techniques used for this, some of which send separate clocks on a separate line, the rest of which encode the clock and data together in various ways as S/PDIF does.
It's pretty neat. IIRC, the way S/PDIF does it is this: it doubles the bit clock rate. At the start of a bit (whether zero or one), the level changes from zero to one or one to zero (depending on the value of the previous bit). Halfway through the bit, if the value is one, the state changes back to the previous state. If the value is zero, it does not change. By doing this, you can watch the stream of bits and even if you don't know the data rate, it takes at most a single one bit for you to figure out the width of a bit. After that, it takes at most a single zero bit to determine which boundary is the half-bit boundary and which one is the full boundary. Once you know that, the state changes from logic low to high and vice versa give you not only the clock, but also the data.
The sad thing is that I wrote this off the top of my head and
then checked Wikipedia because I couldn't remember the name of the encoding....
It's Biphase Mark Code. *sigh*
The upshot of this is that there is a data boundary every so often to indicate where each sample or group of samples begins (no, I don't know the frame size or the framing details up at that level of the stack; it is really just data at that point). From this, because it knows the number of bits per sample, the hardware can divide that bit clock down into something resembling a sample clock....